Fault-tolerant Filter based on an Evolvable Hardware Technique: a case study

This work addresses the problem of providing fault tolerance to an eighth order low-pass filter, employing the principles of evolvable hardware. The filter under study is implemented through the cascade connection of four biquadratic filters in a field programmable analog device. The reconfiguration process of the filter involves the execution of a genetic algorithm (GA) in an external computer, after a fault detected. To perform the test of the filter, we assume that the method of transient analysis is applied. The GA performance is evaluated by fault simulation, employing a parametric fault model. The fault simulation results show that GA finds solutions that meet the established restrictions and presents relatively short run times.